TECHNOLOGY INTEL VIRTUALIZATION

MA'RIFATUN NAFILA

INTEL VIRTUALIZATION TECHNOLOGY

                Salah satu firur teknologi yang di aplikasikan pada mikroprosesor golongan x86 adalah virtualization  .dalam komputasi, x86 adalah fasilitas yang disediakan agar beberapa sistem operasi dapat berjalan (beroperasi) bersamaan sezara simultan pada computer x86, dan dapat berlangsung secara evisien dengan cara yang aman.intel juga menggunakan teknologi ini untuk di aplikasikan pada mikroprosesor buatannya.

                 Teknologi virtualisasi buatan intel untuk platfrom  mikroposesor golongan x86 ini disebut dengan nama intel virtualization technology for x86 dan di angkat menjadi intel vt-x.IVT ini merupakan satu set perangjat keras tambahan yang menjadi platform intel untuk server dank lien yang dapat mengingkatkan solusi virtualisasi. Di dalamnya termasuk EPT (Extended Page Table), yaitu sebuah teknologi untuk virtualisasi tabel halaman (page-table virtualization) yang terdapat di arsitektur Nehalem.

technology UMP

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UMP TECHNOLOGY

Link UMP A100 dan A110 CPU dengan 945GU dan ICH7U north dan south bridge. Sebagai nama menyarankan, mereka berasal dari produk chipset Intel yang ada. A100 dan A110 diyakini 'Dothan' Pentium M chip dengan 512KB L2 cache dan dukungan untuk 400MHz frontside bus kecepatan, dan menggabungkan kondisi tidur yang akan menjadi fitur mendatang 'Santa Rosa' mobile Core 2 Duo revisi.

Tapi tidak ada penurunan output panas prosesor dibandingkan dengan CPU UMPC saat ini, sehingga diharapkan perangkat berbasis UMP untuk memiliki pendinginan aktif di papan.

The 945GU mendukung panel LCD dan dapat host port TV. Memiliki jalur PCI Express untuk GPU diskrit, dan dapat menangani hingga 1GB 400MHz DDR 2 memori. Jembatan selatan memiliki paralel ATA 100 saluran tunggal, HD Audio dan dapat menjadi tuan rumah tiga perangkat PCI.

CPU - nama kode 'Stealy' - mungkin prosesor laptop tweak, tapi penggantinya, 'Silverthorne', sedang "dirancang dari bawah ke atas ... khusus untuk sistem ultra-mobile", kepala ultra-mobilitas Intel, Anand Chandrasekher , kata. Silverthorne adalah sebuah chip 45nm, desain prosesor keenam Intel pada ukuran tersebut.

technology mikroprosesor IDA (intel dynamic acceleration)

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TEKNOLOGI IDA PADA MIKROPROSESOR

A.            Intel Dynamic Acceleration (IDA).
Teknologi ini dibuat untuk meningkatkan kinerja aplikasi-aplikasi single thread, apabila aplikasi-aplikasi tersebut belum mampu memanfaatkan fitur dual core dari prosesor Core 2 Duo. Dengan teknologi ini, aplikasi-aplikasi single thread dapat bekerja lebih cepat.
Jika aplikasi single thread dijalankan, prosesor akan menggunakan dan meng-overclock salah satu core. Pada sisi lain, jika kedua core dalam kondisi aktif (terpakai), prosesor akan mengatur agar thermal (panas) kedua core sama.

B.            Intel teknologi Percepatan Dinamis (IDA) adalah fitur yang meningkatkan kinerja CPU saat CPU menjalankan aplikasi single thread. Hal ini dicapai dengan meningkatnya frekuensi sementara satu inti CPU ketika core CPU lain idle, yaitu ketika kedua inti CPU di Deep Sleep atau kondisi daya rendah. Berapa banyak frekuensi meningkat tergantung pada Front side bus speed dari CPU:

     533 MHz FSB - sebesar 133 MHz
     800 MHz FSB - 200 MHz
     1066 MHz FSB - oleh 133 atau 266 MHz

Fitur ini diperkenalkan pada Intel Core 2 Duo Ponsel mikroprosesor keluarga dan hanya berlaku untuk CPU dual-core. Prosesor quad-core menggabungkan Ganda Dinamis fitur Percepatan, yang bekerja sama dengan IDA. Baru mikroprosesor Intel berbasis Nehalem inti memanfaatkan versi perbaikan dari IDA disebut Turbo Boost Technology.

C.            Intel Percepatan Dinamis (IDA) dari Core 2 Duo CPU dirancang sedemikian rupa sehingga CPU akan menggunakan multiplier yang lebih tinggi (speed cepat) tetapi Intel dirancang fitur ini sehingga hanya satu inti pada suatu waktu bisa mendapatkan keuntungan dari turbo boost ini. Inti kedua harus dalam keadaan sleep C3 / C6 untuk bekerja. Begitu inti kedua bangun untuk memproses beberapa tugas latar belakang; multiplier maksimum akan turun kembali ke multiplier default. Ketika inti kedua adalah selesai dan kembali tidur, inti pertama bisa kembali ke kecepatan yang lebih tinggi dengan beralih ke multiplier IDA.


Modus IDA tersedia di sebagian besar T7000, T8000, P8000 dan seri T9000 Core 2 Duo CPU ponsel.

D.            Intel Dynamic Acceleration (IDA) kadang-kadang disebut Dynamic Percepatan Teknologi (DAT) adalah teknologi yang diciptakan oleh Intel Corp di tertentu Intel mikroprosesor multi-core. Hal ini meningkatkan laju jam dari satu inti untuk setiap dua core di atas frekuensi operasi basis jika core lainnya menganggur. Hal ini dirancang untuk program threaded tunggal untuk berjalan lebih cepat pada multi-core Intel mikroprosesor. Intel kemudian merilis versi IDA disebut ditingkatkan Percepatan Dinamis Teknologi (eDAT) untuk prosesor quad core-nya yang meningkatkan kinerja 2 core ketika hanya 2 core sedang digunakan.

E.            Intel Percepatan Dinamis (IDA) dari Core 2 Duo CPU dirancang sedemikian rupa sehingga CPU akan menggunakan multiplier yang lebih tinggi (speed cepat) tetapi Intel dirancang fitur ini sehingga hanya satu inti pada suatu waktu bisa mendapatkan keuntungan dari turbo boost ini. Inti kedua harus dalam keadaan sleep C3 / C6 untuk bekerja. Begitu inti kedua bangun untuk memproses beberapa tugas latar belakang; multiplier maksimum akan turun kembali ke multiplier default. Ketika inti kedua adalah selesai dan kembali tidur, inti pertama bisa kembali ke kecepatan yang lebih tinggi dengan beralih ke multiplier IDA.

Modus IDA tersedia di sebagian besar T7000, T8000, P8000 dan seri T9000 Core 2 Duo CPU ponsel.

Ada akhirnya cara mudah untuk mengaktifkan modus IDA pada kedua core pada saat yang sama sehingga tidak berputar dan berhenti seperti Intel dimaksudkan. Ketika pengujian pada T8100, ini mengakibatkan peningkatan kinerja 9% ketika menjalankan benchmark wPrime multi-threaded.

Sayangnya, tidak semua laptop mampu mengaktifkan mode Dual IDA. Anda harus mampu untuk mengaktifkan SpeedStep (EIST) bit dari dalam Windows. Pada D830 Dell saya diuji, ada pilihan di bios sehingga Anda dapat menonaktifkan SpeedStep / EIST tetapi banyak produsen mengunci bit EIST dan tidak memberikan pilihan untuk membukanya. Jika Anda tidak memiliki opsi bios ini dan ThrottleStop menunjukkan bahwa bit EIST berwarna abu-abu, itu berarti terkunci dan Anda tidak akan dapat menggunakan trik ini.

F.            Prosesor mendukung modus Intel Percepatan Dinamis Technology. Intel
Fitur dinamis Percepatan Teknologi memungkinkan satu inti dari prosesor untuk beroperasi pada
titik frekuensi yang lebih tinggi ketika core yang lain sedang tidak aktif dan sistem operasi
permintaan peningkatan kinerja. Frekuensi yang lebih tinggi ini disebut oportunistik
frekuensi dan nilai maksimum frekuensi operasi adalah frekuensi terjamin.
Prosesor ini mencakup mekanisme hysteresis yang meningkatkan keseluruhan Intel Dinamis
Percepatan kinerja Teknologi dengan mengurangi transisi yang tidak perlu dari
core masuk dan keluar dari modus Intel Percepatan Dinamis Technology. Biasanya,
prosesor akan keluar Intel Dynamic Acceleration Technology secepat dua core yang
aktif. Hal ini dapat menjadi masalah jika inti menganggur sering terbangun untuk pendek
periode (yaitu, timer tinggi tarif tick). Mekanisme hysteresis memungkinkan dua core menjadi
aktif untuk waktu yang terbatas sebelum transisi dari Intel Dynamic Acceleration
Modus teknologi.
Intel modus Percepatan Dinamis Teknologi memungkinkan membutuhkan:
• Exposure, melalui BIOS, dari frekuensi oportunistik sebagai ACPI P negara tertinggi
• Peningkatan Manajemen Termal Multi-Threaded (EMTTM)
• Modus Intel Dynamic Percepatan Teknologi dan konfigurasi EMTTM MSR melalui BIOS

G.          

technology mikroprosesor SSSE3

Ma'rifatun Nafila

SSSE3

Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.

Contents

• 1 History
• 2 Functionality
• 3 CPUs with SSSE3
• 4 New Instructions
• 5 See also
• 6 References
• 7 External links

History

SSSE3 was first introduced with Intel processors based on the Core microarchitecture on 26 June 2006 with the "Woodcrest" Xeons.

SSSE3 has been referred to by the codenames Tejas New Instructions (TNI) or Merom New Instructions (MNI) for the first processor designs intended to support it.

Functionality

SSSE3 contains 16 new discrete instructions.

Each instruction can act on 64-bit MMX or 128-bit XMM registers. Therefore, Intel's materials refer to 32 new instructions.

According to Intel:

SSSE3 provide 32 instructions (represented by 14 mnemonics) to accelerate computations on packed integers. These include:

• Twelve instructions that perform horizontal addition or subtraction operations.
• Six instructions that evaluate absolute values.
• Two instructions that perform multiply and add operations and speed up the evaluation of dot products.
• Two instructions that accelerate packed-integer multiply operations and produce integer values with scaling.
• Two instructions that perform a byte-wise, in-place shuffle according to the second shuffle control operand.
• Six instructions that negate packed integers in the destination operand if the signs of the corresponding element in the source operand is less than zero.
• Two instructions that align data from the composite of two operands.

CPUs with SSSE3

• AMD:
• Bobcat
• Bulldozer
• Piledriver
• Intel:
• Xeon 5100 Series
• Xeon 5300 Series
• Xeon 3000 Series
• Core 2 Duo
• Core 2 Extreme
• Core 2 Quad
• Core i7
• Core i5
• Core i3
• Pentium Dual Core
• Celeron 4xx Sequence Conroe-L
• Celeron Dual Core E1200
• Celeron M 500 series
• Atom
• VIA:
• Nano

New Instructions

In the table below, satsw(X) (read as 'saturate to signed word') takes a signed integer X, and converts it to −32768 if it's less than −32768, to +32767 if it's greater than 32767, and leaves it unchanged otherwise. As normal for the Intel architecture, bytes are 8 bits, words 16 bits, and dwords 32 bits; 'register' refers to an MMX or XMM vector register.

PSIGNB, PSIGNW, PSIGND	Packed Sign	Negate the elements of a register of bytes, words or dwords if the sign of the corresponding elements of another register is negative.
PABSB, PABSW, PABSD	Packed Absolute Value	Fill the elements of a register of bytes, words or dwords with the absolute values of the elements of another register
PALIGNR	Packed Align Right	take two registers, concatenate their values, and pull out a register-length section from an offset given by an immediate value encoded in the instruction.
PSHUFB	Packed Shuffle Bytes	takes registers of bytes A = [a0 a1 a2 ...] and B = [b0 b1 b2 ...] and replaces A with [ab0 ab1 ab2 ...]; except that it replaces the ith entry with 0 if the top bit of bi is set.
PMULHRSW	Packed Multiply High with Round and Scale	treat the sixteen-bit words in registers A and B as signed 15-bit fixed-point numbers between −1 and 1 (e.g. 0x4000 is treated as 0.5 and 0xa000 as −0.75), and multiply them together with correct rounding.
PMADDUBSW	Multiply and Add Packed Signed and Unsigned Bytes	Take the bytes in registers A and B, multiply them together, add pairs, signed-saturate and store. I.e. [a0 a1 a2 …] pmaddubsw [b0 b1 b2 …] = [satsw(a0b0+a1b1) satsw(a2b2+a3b3) …]
PHSUBW, PHSUBD	Packed Horizontal Subtract (Words or Doublewords)	takes registers A = [a0 a1 a2 …] and B = [b0 b1 b2 …] and outputs [a0−a1 a2−a3 … b0−b1 b2−b3 …]
PHSUBSW	Packed Horizontal Subtract and Saturate Words	like PHSUBW, but outputs [satsw(a0−a1) satsw(a2−a3) … satsw(b0−b1) satsw(b2−b3) …]
PHADDW, PHADDD	Packed Horizontal Add (Words or Doublewords)	takes registers A = [a0 a1 a2 …] and B = [b0 b1 b2 …] and outputs [a0+a1 a2+a3 … b0+b1 b2+b3 …]
PHADDSW	Packed Horizontal Add and Saturate Words	like PHADDW, but outputs [satsw(a0+a1) satsw(a2+a3) … satsw(b0+b1) satsw(b2+b3) …]

See also

• SIMD
• SSE3
• Intel Core 2
• Tejas and Jayhawk
• x86 instruction listings

References

External links

• Core 2 Mobile specifications

• Intel white-paper admitting the existence of SSSE3 and describing SSE4
• Instruction set documentation listing the functions of the SSSE3 instructions

[hide] v t e Multimedia extensions RISC PA-RISC Multimedia Acceleration eXtensions (MAX) SPARC Visual Instruction Set (VIS) MIPS MDMX MIPS-3D Alpha Motion Video Instructions (MVI) Power Architecture AltiVec ARM NEON x86 (current) MMX (1996) 3DNow! (1998) Streaming SIMD Extensions (SSE) (1999) SSE2 (2001) SSE3 (2004) Supplemental SSE3 (SSSE3) (2006) SSE4 (2006) SSE5(2007) Advanced Encryption Standard (AES) (2008) Advanced Vector Extensions (AVX) (2008) F16C (2009 (AMD), 2011 (Intel)) XOP (2009) FMA instructions (FMA4: 2011, FMA3: 2012 (AMD), 2013 (Intel)) Bit manipulation instructions (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012) x86 (planned) AVX-512 (2015) x86 : Instructions (Year Introduced); Italics = AMD exclusive; Year = Superseded

Categories:

• X86 instructions
• SIMD computing

 

Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.

Contents

• 1 History
• 2 Functionality
• 3 CPUs with SSSE3
• 4 New Instructions
• 5 See also
• 6 References
• 7 External links

History

SSSE3 was first introduced with Intel processors based on the Core microarchitecture on 26 June 2006 with the "Woodcrest" Xeons.

SSSE3 has been referred to by the codenames Tejas New Instructions (TNI) or Merom New Instructions (MNI) for the first processor designs intended to support it.

Functionality

SSSE3 contains 16 new discrete instructions.

Each instruction can act on 64-bit MMX or 128-bit XMM registers. Therefore, Intel's materials refer to 32 new instructions.

According to Intel:

SSSE3 provide 32 instructions (represented by 14 mnemonics) to accelerate computations on packed integers. These include:

• Twelve instructions that perform horizontal addition or subtraction operations.
• Six instructions that evaluate absolute values.
• Two instructions that perform multiply and add operations and speed up the evaluation of dot products.
• Two instructions that accelerate packed-integer multiply operations and produce integer values with scaling.
• Two instructions that perform a byte-wise, in-place shuffle according to the second shuffle control operand.
• Six instructions that negate packed integers in the destination operand if the signs of the corresponding element in the source operand is less than zero.
• Two instructions that align data from the composite of two operands.

CPUs with SSSE3

• AMD:
• Bobcat
• Bulldozer
• Piledriver
• Intel:
• Xeon 5100 Series
• Xeon 5300 Series
• Xeon 3000 Series
• Core 2 Duo
• Core 2 Extreme
• Core 2 Quad
• Core i7
• Core i5
• Core i3
• Pentium Dual Core
• Celeron 4xx Sequence Conroe-L
• Celeron Dual Core E1200
• Celeron M 500 series
• Atom
• VIA:
• Nano

New Instructions

In the table below, satsw(X) (read as 'saturate to signed word') takes a signed integer X, and converts it to −32768 if it's less than −32768, to +32767 if it's greater than 32767, and leaves it unchanged otherwise. As normal for the Intel architecture, bytes are 8 bits, words 16 bits, and dwords 32 bits; 'register' refers to an MMX or XMM vector register.

PSIGNB, PSIGNW, PSIGND	Packed Sign	Negate the elements of a register of bytes, words or dwords if the sign of the corresponding elements of another register is negative.
PABSB, PABSW, PABSD	Packed Absolute Value	Fill the elements of a register of bytes, words or dwords with the absolute values of the elements of another register
PALIGNR	Packed Align Right	take two registers, concatenate their values, and pull out a register-length section from an offset given by an immediate value encoded in the instruction.
PSHUFB	Packed Shuffle Bytes	takes registers of bytes A = [a0 a1 a2 ...] and B = [b0 b1 b2 ...] and replaces A with [ab0 ab1 ab2 ...]; except that it replaces the ith entry with 0 if the top bit of bi is set.
PMULHRSW	Packed Multiply High with Round and Scale	treat the sixteen-bit words in registers A and B as signed 15-bit fixed-point numbers between −1 and 1 (e.g. 0x4000 is treated as 0.5 and 0xa000 as −0.75), and multiply them together with correct rounding.
PMADDUBSW	Multiply and Add Packed Signed and Unsigned Bytes	Take the bytes in registers A and B, multiply them together, add pairs, signed-saturate and store. I.e. [a0 a1 a2 …] pmaddubsw [b0 b1 b2 …] = [satsw(a0b0+a1b1) satsw(a2b2+a3b3) …]
PHSUBW, PHSUBD	Packed Horizontal Subtract (Words or Doublewords)	takes registers A = [a0 a1 a2 …] and B = [b0 b1 b2 …] and outputs [a0−a1 a2−a3 … b0−b1 b2−b3 …]
PHSUBSW	Packed Horizontal Subtract and Saturate Words	like PHSUBW, but outputs [satsw(a0−a1) satsw(a2−a3) … satsw(b0−b1) satsw(b2−b3) …]
PHADDW, PHADDD	Packed Horizontal Add (Words or Doublewords)	takes registers A = [a0 a1 a2 …] and B = [b0 b1 b2 …] and outputs [a0+a1 a2+a3 … b0+b1 b2+b3 …]
PHADDSW	Packed Horizontal Add and Saturate Words	like PHADDW, but outputs [satsw(a0+a1) satsw(a2+a3) … satsw(b0+b1) satsw(b2+b3) …]

See also

• SIMD
• SSE3
• Intel Core 2
• Tejas and Jayhawk
• x86 instruction listings

References

External links

• Core 2 Mobile specifications

• Intel white-paper admitting the existence of SSSE3 and describing SSE4
• Instruction set documentation listing the functions of the SSSE3 instructions

[hide] v t e Multimedia extensions RISC PA-RISC Multimedia Acceleration eXtensions (MAX) SPARC Visual Instruction Set (VIS) MIPS MDMX MIPS-3D Alpha Motion Video Instructions (MVI) Power Architecture AltiVec ARM NEON x86 (current) MMX (1996) 3DNow! (1998) Streaming SIMD Extensions (SSE) (1999) SSE2 (2001) SSE3 (2004) Supplemental SSE3 (SSSE3) (2006) SSE4 (2006) SSE5(2007) Advanced Encryption Standard (AES) (2008) Advanced Vector Extensions (AVX) (2008) F16C (2009 (AMD), 2011 (Intel)) XOP (2009) FMA instructions (FMA4: 2011, FMA3: 2012 (AMD), 2013 (Intel)) Bit manipulation instructions (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012) x86 (planned) AVX-512 (2015) x86 : Instructions (Year Introduced); Italics = AMD exclusive; Year = Superseded

Categories:

• X86 instructions
• SIMD computing

Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.

Contents

• 1 History
• 2 Functionality
• 3 CPUs with SSSE3
• 4 New Instructions
• 5 See also
• 6 References
• 7 External links

History

SSSE3 was first introduced with Intel processors based on the Core microarchitecture on 26 June 2006 with the "Woodcrest" Xeons.

SSSE3 has been referred to by the codenames Tejas New Instructions (TNI) or Merom New Instructions (MNI) for the first processor designs intended to support it.

Functionality

SSSE3 contains 16 new discrete instructions.

Each instruction can act on 64-bit MMX or 128-bit XMM registers. Therefore, Intel's materials refer to 32 new instructions.

According to Intel:

SSSE3 provide 32 instructions (represented by 14 mnemonics) to accelerate computations on packed integers. These include:

• Twelve instructions that perform horizontal addition or subtraction operations.
• Six instructions that evaluate absolute values.
• Two instructions that perform multiply and add operations and speed up the evaluation of dot products.
• Two instructions that accelerate packed-integer multiply operations and produce integer values with scaling.
• Two instructions that perform a byte-wise, in-place shuffle according to the second shuffle control operand.
• Six instructions that negate packed integers in the destination operand if the signs of the corresponding element in the source operand is less than zero.
• Two instructions that align data from the composite of two operands.

CPUs with SSSE3

• AMD:
• Bobcat
• Bulldozer
• Piledriver
• Intel:
• Xeon 5100 Series
• Xeon 5300 Series
• Xeon 3000 Series
• Core 2 Duo
• Core 2 Extreme
• Core 2 Quad
• Core i7
• Core i5
• Core i3
• Pentium Dual Core
• Celeron 4xx Sequence Conroe-L
• Celeron Dual Core E1200
• Celeron M 500 series
• Atom
• VIA:
• Nano

New Instructions

In the table below, satsw(X) (read as 'saturate to signed word') takes a signed integer X, and converts it to −32768 if it's less than −32768, to +32767 if it's greater than 32767, and leaves it unchanged otherwise. As normal for the Intel architecture, bytes are 8 bits, words 16 bits, and dwords 32 bits; 'register' refers to an MMX or XMM vector register.

PSIGNB, PSIGNW, PSIGND	Packed Sign	Negate the elements of a register of bytes, words or dwords if the sign of the corresponding elements of another register is negative.
PABSB, PABSW, PABSD	Packed Absolute Value	Fill the elements of a register of bytes, words or dwords with the absolute values of the elements of another register
PALIGNR	Packed Align Right	take two registers, concatenate their values, and pull out a register-length section from an offset given by an immediate value encoded in the instruction.
PSHUFB	Packed Shuffle Bytes	takes registers of bytes A = [a0 a1 a2 ...] and B = [b0 b1 b2 ...] and replaces A with [ab0 ab1 ab2 ...]; except that it replaces the ith entry with 0 if the top bit of bi is set.
PMULHRSW	Packed Multiply High with Round and Scale	treat the sixteen-bit words in registers A and B as signed 15-bit fixed-point numbers between −1 and 1 (e.g. 0x4000 is treated as 0.5 and 0xa000 as −0.75), and multiply them together with correct rounding.
PMADDUBSW	Multiply and Add Packed Signed and Unsigned Bytes	Take the bytes in registers A and B, multiply them together, add pairs, signed-saturate and store. I.e. [a0 a1 a2 …] pmaddubsw [b0 b1 b2 …] = [satsw(a0b0+a1b1) satsw(a2b2+a3b3) …]
PHSUBW, PHSUBD	Packed Horizontal Subtract (Words or Doublewords)	takes registers A = [a0 a1 a2 …] and B = [b0 b1 b2 …] and outputs [a0−a1 a2−a3 … b0−b1 b2−b3 …]
PHSUBSW	Packed Horizontal Subtract and Saturate Words	like PHSUBW, but outputs [satsw(a0−a1) satsw(a2−a3) … satsw(b0−b1) satsw(b2−b3) …]
PHADDW, PHADDD	Packed Horizontal Add (Words or Doublewords)	takes registers A = [a0 a1 a2 …] and B = [b0 b1 b2 …] and outputs [a0+a1 a2+a3 … b0+b1 b2+b3 …]
PHADDSW	Packed Horizontal Add and Saturate Words	like PHADDW, but outputs [satsw(a0+a1) satsw(a2+a3) … satsw(b0+b1) satsw(b2+b3) …]

See also

• SIMD
• SSE3
• Intel Core 2
• Tejas and Jayhawk
• x86 instruction listings

References

External links

• Core 2 Mobile specifications

• Intel white-paper admitting the existence of SSSE3 and describing SSE4
• Instruction set documentation listing the functions of the SSSE3 instructions

[hide] v t e Multimedia extensions RISC PA-RISC Multimedia Acceleration eXtensions (MAX) SPARC Visual Instruction Set (VIS) MIPS MDMX MIPS-3D Alpha Motion Video Instructions (MVI) Power Architecture AltiVec ARM NEON x86 (current) MMX (1996) 3DNow! (1998) Streaming SIMD Extensions (SSE) (1999) SSE2 (2001) SSE3 (2004) Supplemental SSE3 (SSSE3) (2006) SSE4 (2006) SSE5(2007) Advanced Encryption Standard (AES) (2008) Advanced Vector Extensions (AVX) (2008) F16C (2009 (AMD), 2011 (Intel)) XOP (2009) FMA instructions (FMA4: 2011, FMA3: 2012 (AMD), 2013 (Intel)) Bit manipulation instructions (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012) x86 (planned) AVX-512 (2015) x86 : Instructions (Year Introduced); Italics = AMD exclusive; Year = Superseded

Categories:

• X86 instructions
• SIMD computing